Plasma Display Panels (PDPs) that display video signals using discharging phenomena may be categorized as DC types (DC PDPs) and AC types (AC PDPs) according to their driving voltages. AC PDPs are getting popular because DC PDPs have a complex structure and have low efficiency and a short life span.
As shown in FIG. 1, a typical AC PDP includes a plurality of layers, and it has spatial merits because it is thin and light and can provide a larger display area than more conventional display devices, such as a CRT.
As shown in FIG. 1, the principal structure of an AC PDP includes scan electrodes 4, sustain electrodes 5, a dielectric layer 2, a protecting layer 3, and an insulating layer 7, all of which are arranged between a first glass substrate 1 at an uppermost location and a second glass substrate 6 at a lowermost location. Discharge cells 12 are located on the first glass substrate 1.
The pair of a scan electrode 4 and a sustain electrode 5 between the first glass substrate 1 and the dielectric layer 2 are aligned vertically and parallel with each other. Address electrodes 8 covered with the insulating layer 7 are aligned laterally on the second glass substrate 6 and are approximately perpendicular to the scan electrodes 4 and the sustain electrodes 5. A discharge cell 12 is formed, as a discharging area, at a location where one address electrode 8 meets the scan electrode 4 and the sustain electrode 5. Barrier ribs 9 are formed parallel to the address electrodes 8 on the insulating layer 7. In addition, phosphor 10 is formed on the surface of the insulating layer 7 and on both sides of the barrier ribs 9.
Therefore, as shown in FIG. 2, the discharge cells 12 are arranged in a matrix pattern according to the scan electrodes 4, sustain electrodes 5, and the address electrodes 8.
Improving contrast, among a variety of features, takes an important role in improving the display quality of a PDP having such a structure. The contrast of an image displayed on the PDP is expressed as a ratio of luminance at the state of no discharging, which is darkest, to a luminance at the peak white state, which is brightest. The light in the peak white state is achieved mainly by a sustain discharge, and the darkest portion is when there is no sustain discharge. However, every cell goes through discharge in the initializing step.
Therefore, improvement of the contrast may be achieved by enhancing the brightness of the brightest portion or by reducing the brightness of the darkest portion. The contrast is also improved if a background luminance in the state of no discharging is lowered.
One field of a signal for driving such an AC PDP usually includes 8 to 12 subfields, where each subfield may be divided into 4 periods of a reset period, an address period, a sustain period, and an erase period.
The address period is a period where actual data is applied. During the address period, cells to be activated are selected and wall charges are accumulated in the selected cells. The reset period is a period for initializing each cell before the address period to ensure application of data in the address period.
The sustain period is a period where discharge takes place in order to actually display a video signal at the cells addressed in the address period. In the erase period, the sustain discharge is terminated by reducing the wall charges of the cells.
FIG. 3 shows a conventional pattern of driving signals for a PDP according to the prior art.
As shown in FIG. 3, the sustain electrode X is kept at its ground voltage in the reset period while a signal applied to the scan electrode Y is increased linearly in a rising ramp period.
At this time, a weak discharge takes place between the address electrode A and the scan electrode Y. As a result, positive wall charges are accumulated at the address electrode A and negative wall charges are accumulated at the scan electrode Y. A small amount of positive charge is also accumulated at the sustain electrode X because the sustain electrode is maintained at its ground voltage.
An initialization discharge that occurs during the rising ramp period is hereinafter described in detail.
During the rising ramp period, a weak discharge between the address electrode A and the scan electrode Y becomes a primary discharge. As a result, positive charges are accumulated at the address electrode A and the sustain electrode X, and negative charges are accumulated at the scan electrode Y.
The sustain electrode X functions as a cathode in the discharge among the address electrode A, the sustain electrode X, and the scan electrode Y, because the sustain electrode X is also maintained at its ground voltage. Therefore, the sustain electrode X also gathers positive charges.
During a falling ramp period that follows the rising ramp period, the positive charges of the address electrode A are maintained, and the positive charges of the sustain electrode X are eliminated by a discharge between the sustain electrode X and the scan electrode Y. During this falling ramp period, negative charges accumulated at the scan electrode Y are in part transferred to the sustain electrode X.
For an AC PDP having 12 subfields, the total luminance in such a reset period is approximately 1.0 to 1.2 cd/m2. Therefore, supposing that the luminance at the brightest state is 500 cd, a contrast ratio in a darkroom would be approximately 420:1 to 500:1, which is low.
In addition, during the reset period, a voltage of 0 (zero) volts is applied to the address electrode A regardless of the color of the phosphor.
FIG. 4 illustrates the driving signals of FIG. 3 for the scan electrode Y and the sustain electrode X together in the same plane during the reset period.
As shown in FIG. 4, the driving voltage Vx applied to the sustain electrode X maintains its ground voltage of 0 (zero) volts while the driving voltage Vy applied to the scan electrode Y remains in a rising ramp period (refer to region a).
At the moment that the driving voltage Vy applied to the scan electrode Y is lowered to a voltage Vs, the driving voltage Vx applied to the sustain electrode X is increased to a voltage Ve. In an intermediate region b, the driving voltage Vx, of the sustain electrode X is maintained to be higher than the driving voltage Vy of the scan electrode Y.
After the intermediate region b, the driving voltage Vy applied to the scan electrode Y is reduced from the voltage Vs to the ground voltage following a pattern of a falling ramp.
FIG. 5 illustrates charges accumulated at each of the electrodes according to regions of the reset period shown in FIG. 4.
In a stage S100 that corresponds to the region a in FIG. 4, the voltage of the scan electrode Y rises up to 380 V following a ramp pattern, and the sustain electrode X and the address electrode A are maintained at their ground voltages.
At this time, a weak discharge occurring between the address electrode A and the scan electrode Y becomes a primary discharge. As a result, positive charges are accumulated at the address electrode A and the sustain electrode X, and negative charges are accumulated at the scan electrode Y.
The sustain electrode X functions as a cathode in the discharge among the address electrode A, the sustain electrode X, and the scan electrode Y, because the sustain electrode X is also maintained at its ground voltage. Therefore, the sustain electrode X also gathers positive charges.
Stage S110 shows a state immediately after entering the region b. At this time, the driving voltage for the sustain electrode X is, for example, 195V, and the driving voltage for the scan electrode Y is reduced, for example, to 165V.
The illustration for the stage S120 shows distribution and movement of wall charges in the region b.
In the region b, the driving voltage Vx applied to the sustain electrode X is increased to a voltage Ve at the moment that the driving voltage Vy applied to the scan electrode Y is lowered to a voltage Vs. Subsequently, the voltage of the scan electrode Y is maintained to be lower than the voltage of the sustain voltage.
At the start of the region b, negative wall charges are accumulated at the scan electrode Y since this is immediately after the rising ramp period of the driving voltage, and positive wall charges are accumulated at the sustain electrode X (refer to S110).
Therefore, applying a voltage to the sustain electrode X that is higher than that applied to the scan electrode Y causes an offset of the positive charges at the sustain electrode X and the negative charges of the scan electrode Y, and as a result, generating self-erasing light.
With such a self-erasing light, wall charge distribution of the sustain electrode X and scan electrode Y becomes opposite to that of the moment when starting the region b. In this situation, a mal-discharge may occur because a sustain discharge may be induced when an address signal is not yet applied.
While such a mal-discharge is occurring, positive charges are accumulated at the scan electrode Y and negative charges are accumulated at the sustain electrode X, which may result in failure of an address discharge and an occurrence of mal-discharge in the sustain period before the address period.
In addition, according to the prior art described above, in the case that such a self-erasing light occurs, an over-discharge may occur in a low gray state wherein the number of discharging subfields is small, and accordingly, the contrast of display becomes unstable.